In digital systems that include multiplexers, an output signal is generated from two or more data inputs and one or more select signals. The number of data or clock inputs "n" is less than or equal to 2.sup.k, where k=the number of select inputs. In a standard multiplexer, once the select input(s) change, the output will begin to reflect the newly selected data input as soon as the select input propagates through the internal logic. If the data input signals being selected are asynchronous to each other, the output pulse width or duration may be narrower than the narrowest data input pulse width. This is called a "glitch", which can cause substantial problems in digital systems. Any sub-minimum pulse width can violate the timing specification and requirements for other elements in the system causing a variety of operational malfunctions which may range from transitory to more permanent crashes.
In particular, a glitch can be any clock pulse or duration, either high or low, that is shorter in duration than the corresponding pulse of the input clock before or after the clock selection switching. For example, if the system is currently synchronized on a clock of 100 MHz and a switch is made to a clock system of 125 MHz, both clocks having a 50% duty cycle, no clock pulse of duration shorter than four nanoseconds can be generated during selection switching without otherwise resulting in a glitch. Thus a need exists for a method of switching from one clock signal to another clock signal without generating a glitch in the output signal.